其中考

module top;
wire a,b,c,d,f;
system_clock #400 clock1(a);
system_clock #200 clock1(b);
system_clock #100 clock1(c);
system_clock #50 clock1(d);
exam AXEM1(a,b,c,d,f);
endmodule

module exam(a,b,c,d,f);
input a,b,c,d;
output f;
wire f1,f2,f3,f4;
and M1(f1,~a,~c,~d);
and M2(f2,~a,b,d);
and M3(f3,a,b,~d);
and M4(f4,~b,c,~d);
or(f,f1,f2,f3,f4);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule