16位元加法器(行為模式)

module top;
wire [16:1]a,b,sum;
wire c_in,c_out;
system_clock #1 clock1(a[1]);
system_clock #2 clock1(a[2]);
system_clock #4 clock1(a[3]);
system_clock #8 clock1(a[4]);
system_clock #16 clock1(a[5]);
system_clock #32 clock1(a[6]);
system_clock #64 clock1(a[7]);
system_clock #128 clock1(a[8]);
system_clock #256 clock1(a[9]);
system_clock #512 clock1(a[10]);
system_clock #1024 clock1(a[11]);
system_clock #2048 clock1(a[12]);
system_clock #4096 clock1(a[13]);
system_clock #8192 clock1(a[14]);
system_clock #16384 clock1(a[15]);
system_clock #32768 clock1(a[16]);

system_clock #32768 clock1(b[1]);
system_clock #16384 clock1(b[2]);
system_clock #8192 clock1(b[3]);
system_clock #4096 clock1(b[4]);
system_clock #2048 clock1(b[5]);
system_clock #1024 clock1(b[6]);
system_clock #512 clock1(b[7]);
system_clock #256 clock1(b[8]);
system_clock #128 clock1(b[9]);
system_clock #64 clock1(b[10]);
system_clock #32 clock1(b[11]);
system_clock #16 clock1(b[12]);
system_clock #8 clock1(b[13]);
system_clock #4 clock1(b[14]);
system_clock #2 clock1(b[15]);
system_clock #1 clock1(b[16]);
system_clock #5000000 clock1(c_in);
Add_full_16 ADD(sum,c_out,a,b,c_in);
endmodule

module Add_full_16(sum,c_out,a,b,c_in);
input [16:1]a,b;
input c_in;
output [16:1]sum;
output c_out;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>33000)#(PERIOD-1)$stop;
endmodule