16位元加法器(行為模式)

module top;
wire [16:1]a,b,sum;
wire c_in,c_out;
system_clock #1 clock1(a[1]);
system_clock #2 clock1(a[2]);
system_clock #4 clock1(a[3]);
system_clock #8 clock1(a[4]);
system_clock #16 clock1(a[5]);
system_clock #32 clock1(a[6]);
system_clock #64 clock1(a[7]);
system_clock #128 clock1(a[8]);
system_clock #256 clock1(a[9]);
system_clock #512 clock1(a[10]);
system_clock #1024 clock1(a[11]);
system_clock #2048 clock1(a[12]);
system_clock #4096 clock1(a[13]);
system_clock #8192 clock1(a[14]);
system_clock #16384 clock1(a[15]);
system_clock #32768 clock1(a[16]);

system_clock #32768 clock1(b[1]);
system_clock #16384 clock1(b[2]);
system_clock #8192 clock1(b[3]);
system_clock #4096 clock1(b[4]);
system_clock #2048 clock1(b[5]);
system_clock #1024 clock1(b[6]);
system_clock #512 clock1(b[7]);
system_clock #256 clock1(b[8]);
system_clock #128 clock1(b[9]);
system_clock #64 clock1(b[10]);
system_clock #32 clock1(b[11]);
system_clock #16 clock1(b[12]);
system_clock #8 clock1(b[13]);
system_clock #4 clock1(b[14]);
system_clock #2 clock1(b[15]);
system_clock #1 clock1(b[16]);
system_clock #5000000 clock1(c_in);
Add_full_16 ADD(sum,c_out,a,b,c_in);
endmodule

module Add_full_16(sum,c_out,a,b,c_in);
input [16:1]a,b;
input c_in;
output [16:1]sum;
output c_out;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>33000)#(PERIOD-1)$stop;
endmodule

16位元加法器(結構模式)

module top;
wire [16:1]a,b,sum;
wire c_out,c_in;
system_clock #1 clock1(a[1]);
system_clock #2 clock1(a[2]);
system_clock #4 clock1(a[3]);
system_clock #8 clock1(a[4]);
system_clock #16 clock1(a[5]);
system_clock #32 clock1(a[6]);
system_clock #64 clock1(a[7]);
system_clock #128 clock1(a[8]);
system_clock #256 clock1(a[9]);
system_clock #512 clock1(a[10]);
system_clock #1024 clock1(a[11]);
system_clock #2048 clock1(a[12]);
system_clock #4096 clock1(a[13]);
system_clock #8192 clock1(a[14]);
system_clock #16384 clock1(a[15]);
system_clock #32768 clock1(a[16]);

system_clock #32768 clock1(b[1]);
system_clock #16384 clock1(b[2]);
system_clock #8192 clock1(b[3]);
system_clock #4096 clock1(b[4]);
system_clock #2048 clock1(b[5]);
system_clock #1024 clock1(b[6]);
system_clock #512 clock1(b[7]);
system_clock #256 clock1(b[8]);
system_clock #128 clock1(b[9]);
system_clock #64 clock1(b[10]);
system_clock #32 clock1(b[11]);
system_clock #16 clock1(b[12]);
system_clock #8 clock1(b[13]);
system_clock #4 clock1(b[14]);
system_clock #2 clock1(b[15]);
system_clock #1 clock1(b[16]);
system_clock #5000000 clock1(c_in);
Add_full_16 ADD(sum,c_out,a,b,c_in);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;

Add_half1 M1(w1,w2,a,b);
Add_half1 M2(sum,w3,w1,c_in);
or(c_out,w3,w2);
endmodule

module Add_full_4(sum,c_out,a,b,c_in);
input [4:1]a,b;
input c_in;
output [4:1]sum;
output c_out;
wire r1,r2,r3;

Add_full X1(sum[1],r1,a[1],b[1],c_in);
Add_full X2(sum[2],r2,a[2],b[2],r1);
Add_full X3(sum[3],r3,a[3],b[3],r2);
Add_full X4(sum[4],c_out,a[4],b[4],r3);
endmodule

module Add_full_16(sum,c_out,a,b,c_in);
input [16:1]a,b;
input c_in;
output [16:1]sum;
output c_out;
wire s1,s2,s3;

Add_full_4 x1(sum[4:1],s1,a[4:1],b[4:1],c_in);
Add_full_4 x2(sum[8:5],s2,a[8:5],b[8:5],s1);
Add_full_4 x3(sum[12:9],s3,a[12:9],b[12:9],s2);
Add_full_4 x4(sum[16:13],c_out,a[16:13],b[16:13],s3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>33000)#(PERIOD-1)$stop;
endmodule

四位元全加器(另一種行為模式)

module top;
wire [4:1]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[1]);
system_clock #200 clock1(a[2]);
system_clock #100 clock1(a[3]);
system_clock #50 clock1(a[4]);
system_clock #600 clock1(b[1]);
system_clock #300 clock1(b[2]);
system_clock #150 clock1(b[3]);
system_clock #75 clock1(b[4]);
system_clock #5000 clock1(c_in);
Add_full ADD(sum,c_out,a,b,c_in);
endmodule

module Add_full(sum,c_out,a,b,c_in);
input [4:1]a,b,c_in;
output [4:1]sum;
output c_out;

assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

四位元全加器 (行為模式)

module top;
wire [4:1]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[1]);
system_clock #200 clock1(a[2]);
system_clock #100 clock1(a[3]);
system_clock #50 clock1(a[4]);
system_clock #600 clock1(b[1]);
system_clock #300 clock1(b[2]);
system_clock #150 clock1(b[3]);
system_clock #75 clock1(b[4]);
system_clock #5000 clock1(c_in);
Add_full_4 addfull4(sum,c_out,a,b,c_in);
endmodule

module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;

assign{c_out,sum}=a+b+c_in;

endmodule


module Add_full_4(sum,c_out,a,b,c_in);
input [4:1]a,b;
input c_in;
output [4:1]sum;
output c_out;
wire r1,r2,r3;

Add_full X1(sum[1],r1,a[1],b[1],c_in);
Add_full X2(sum[2],r2,a[2],b[2],r1);
Add_full X3(sum[3],r3,a[3],b[3],r2);
Add_full X4(sum[4],c_out,a[4],b[4],r3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

四位元全加器(結構模式)

module top;
wire [4:1]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[1]);
system_clock #200 clock1(a[2]);
system_clock #100 clock1(a[3]);
system_clock #50 clock1(a[4]);
system_clock #600 clock1(b[1]);
system_clock #300 clock1(b[2]);
system_clock #150 clock1(b[3]);
system_clock #75 clock1(b[4]);
system_clock #5000 clock1(c_in);
Add_full_4 addfull4(sum,c_out,a,b,c_in);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;

Add_half1 M1(w1,w2,a,b);
Add_half1 M2(sum,w3,w1,c_in);
or(c_out,w3,w2);
endmodule

module Add_full_4(sum,c_out,a,b,c_in);
input [4:1]a,b;
input c_in;
output [4:1]sum;
output c_out;
wire r1,r2,r3;

Add_full X1(sum[1],r1,a[1],b[1],c_in);
Add_full X2(sum[2],r2,a[2],b[2],r1);
Add_full X3(sum[3],r3,a[3],b[3],r2);
Add_full X4(sum[4],c_out,a[4],b[4],r3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

一位元全加法器(結構模式)

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_hull Add1(sum,c_out,a,b,c_in);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module Add_hull(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;

Add_half1 M1(w1,w2,a,b);
Add_half1 M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加器(結構模式)

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half1 addhalf(sum,c_out,a,b);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

4位元加法器

module top;
wire [3:0]sum,a,b;
wire c_out,c_in;
system_clock #10 clock1(a[0]);
system_clock #20 clock1(a[1]);
system_clock #40 clock1(a[2]);
system_clock #80 clock1(a[3]);
system_clock #5 clock1(b[0]);
system_clock #10 clock1(b[1]);
system_clock #20 clock1(b[2]);
system_clock #40 clock1(b[3]);
system_clock #1000 clock1(c_in);
adder_4_RTL adder_4(sum,c_out,a,b,c_in);
endmodule

module adder_4_RTL(sum,c_out,a,b,c_in);
output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;
assign{c_out,sum}=a+b+c_in;
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

D typ 正反器

module top;
wire date_in,clk,rst;
wire q;
system_clock #100 clock1(date_in);
system_clock #50 clock1(clk);
system_clock #1000 clock1(rst);
Filp_flop Filp_flop1(q,date_in,clk,rst);
endmodule

module Filp_flop(q,date_in,clk,rst);
input date_in,clk,rst;
output q;
reg q;
always@(posedge clk)
begin
if(rst==1) q=0;
else q=date_in;
end
endmodule


module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire sum,c;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half myAdd1(sum,c,a,b);
endmodule

module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule