一位元全加法器(結構模式)

module top;
wire a,b,c_in;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_hull Add1(sum,c_out,a,b,c_in);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module Add_hull(sum,c_out,a,b,c_in);
input a,b,c_in;
output sum,c_out;
wire w1,w2,w3;

Add_half1 M1(w1,w2,a,b);
Add_half1 M2(sum,w3,w1,c_in);
or(c_out,w2,w3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule