四位元全加器(結構模式)

module top;
wire [4:1]a,b,sum;
wire c_out,c_in;
system_clock #400 clock1(a[1]);
system_clock #200 clock1(a[2]);
system_clock #100 clock1(a[3]);
system_clock #50 clock1(a[4]);
system_clock #600 clock1(b[1]);
system_clock #300 clock1(b[2]);
system_clock #150 clock1(b[3]);
system_clock #75 clock1(b[4]);
system_clock #5000 clock1(c_in);
Add_full_4 addfull4(sum,c_out,a,b,c_in);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module Add_full(sum,c_out,a,b,c_in);
input a,b,c_in;
output c_out,sum;
wire w1,w2,w3;

Add_half1 M1(w1,w2,a,b);
Add_half1 M2(sum,w3,w1,c_in);
or(c_out,w3,w2);
endmodule

module Add_full_4(sum,c_out,a,b,c_in);
input [4:1]a,b;
input c_in;
output [4:1]sum;
output c_out;
wire r1,r2,r3;

Add_full X1(sum[1],r1,a[1],b[1],c_in);
Add_full X2(sum[2],r2,a[2],b[2],r1);
Add_full X3(sum[3],r3,a[3],b[3],r2);
Add_full X4(sum[4],c_out,a[4],b[4],r3);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule