半加器(結構模式)

module top;
wire a,b;
wire sum,c_out;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half1 addhalf(sum,c_out,a,b);
endmodule

module Add_half1(sum,c_out,a,b);
input a,b;
output sum,c_out;
wire c_out_bar;

xor(sum,a,b);
nand(c_out_bar,a,b);
not(c_out,c_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule